Full Bridge Gate Driver Ic
IntroductionIn the of the series we’ve gone through the high-level design decisions that you have to make when designing an H-Bridge, and we’ve discussed the considerations for selecting the MOSFETs and the catch diodes that will make up the bridge.In this article I will go through the available options for drive circuits. We will discuss the trade-offs between them and what influences the various parameters of the drive circuits.You will take the most out of this write-up if you are already fairly familiar with H-Bridge basics, so if you aren’t, I suggest you read the of the series first. Understanding of the various drive-modes will also be useful, so reading the, the and the articles isn’t a waste of time either, though those pieces go into quite a bit of more detail than what is needed to follow this text.To make referencing easier, let’s review the H-Bridge circuit:and our motor model:Drive circuitryThe drive circuitry for an H-Bridge is basically the electronics that sits between the PWM (and potentially other) digital control inputs and the MOSFET gates. Thank you very much.
Really very informative!I just have a question about N-MOS high-side drive circuits:Is it possible to apply a second voltage higher than Vbat from a second power supply. I mean if the main power supply is 40v,there should be another one higher no more than 20v (55v) to drive the N-MOS high-side gate?I did the simulation and it worked.
I will try that sooner in real.while googling I didn’t find info about this. Does it have any disadvantages apart cost?? Like in turn off, turn on shoot through? Short answer:Don’t try it! It will blow your FET.Long answer:Well, actually it is possible to do and for low voltages that’s quite common. For example (DC-DC power supplies are actually quite close to H-bridges in this regard) old PC motherboards, where the CPU core voltage was regulated down from 5V, the high-side drivers were often driven from 12V.
Exactly what you’re saying.Doing this above, say 20V however is getting tricky: the problem is that the source of the high-side N-FET is connected to the load. When the low-side is on, it drags the high-side source to (close to) GND.
Now, when you get to turn on the high-side FET, you apply in your example 50V to the gate, while the source is at GND. Not many MOSFETs can survive that, most of them are specified for a Vgs no more than +-20V, maybe even less.In other words, you will only be able to use your technique when Vbat (the power supply to the bridge and the load) is less than Vgsmax-Vgson. To turn a high-power MOSFET on, you need a Vgs = 10V or so, and if Vgsmax is (say) 20V, than you can only use your idea with Vbat. Really I thank you very much for such information.and your answer. I spent last night in your site reading and reading.till now I am always connected to it. I have many tabs in my firefox:).I even repeated reading and I will do till I understand.What I need about mosfet and h-bridge is really explained very well and in an easy way. Thanks again for your answer.About H BRIDGE I don’t want ready made IC to drive the N-MOS.i want to experiment by myself like you did:).I want to drive bipolar stepper motor with all possible options like chopper and microstep but without ready made IC.and with variable powerfull power supply till 50v to test various stepper motors, I want use only P&N MOS as driver.
Bridge Gate Community School
Before being in your site I was reading a lot elsewhere,but last night your site explained to me many things,and I know now why I already blew many FETsbefore 🙂. I’ve been working on something similar, and posted it on the Arduino Forums for extra tips, as well as fixing an enormous D-S voltage drop I experience in simulation.I’m getting a lot of flak about tying the gates together, and everyone is saying my schematic is total garbage. I actually haven’t received any of the information I was looking for. I’m getting some good information, like a potential short caused by the two mosfets switching simultaneously. But other than that, the Arduino Forums, in my experience, are more likely to insult you for trying. Hi,very interesting and useful article! My congratulations.Just one note regarding the high side PMOS driver.I’ve used a different (actually quite common) technique: starting from a standard 5V logic buffer (with all the output connected in parallel like in your 74AHC04 example), I’ve first AC-coupled the output and then hooked it to the Vbat rail through a diode (plus some protection/limiting resistors) to clamp any voltage over Vbat; this way the VGS is -5V and the PMOS is properly turned on/off.
This seems to work pretty fine in simulations and overtakes the asymmetrical driver strength issue due to any external resistor. Hi Andras,for what I know the main drawback of the bootstrap-like drivers is the negative voltage spikes they can tolerate on the source terminal, so basically they cannot be used at all in an application where you need split supply (positive and negative) at the bridge legs.Are you aware of any suitable drivers for such kind of applications?
I found some parts form IR (like this: ) specifically suited for D-class amp applications, but I was wandering if any other standard drivers were available.Thank youMaurizio. Hi,I really like this article, it’s very well written and really beginner friendly!In calculating turn-on and turn-off times part, you say:“You can easily see that for the case of driving high voltages, the current source is at around 17mA, and the resistance is around 100Ω. When the output drives low, it can output 21mA and has roughly 70Ω resistance. (It is typical that an output stage has a somewhat weaker high-side driver, being a P-MOS device.)”Where do you read that the resistance is around 100 ohms? I cannot undertand if you see it somewhere on the chart or I just missed an obvious calculation you made?Thanks again!bilo. I have to questions:1- How do we find the output resistance of gate driver that does not provide you with output voltage and current in the same graph?
For example this gate drive IR2106, I calculated the output resistance from the static characteristic, is that correct?2- Why do we have to operate in the linear region not the saturation? Couple of website they recommended to operate in saturation region. I have been looking for the purpose and I barely found a solid answer, could you please talk about it a little in deep? I see why we have to operate in the lower side since we do not have negative voltage applied on the gate (etc Vd = 0V, Vs = 0 and Vg = 0V or 5V) but the high side could be operated in saturation (etc Vd = 12V, Vs = 12 and Vg =.
1 – yes, that’s the best you can probably go by and it’s a good first-order estimate.2 – operating in a saturation region is sub-optimal: notice how the curve drops lower then a straight line. That means that the effective resistance of the FET increases, so you burn more and more power on the FET, making it hotter and lowering bridge efficiency.
The curve also quickly levels off at a constant current. That means you can’t increase the output power of the bridge any further.One benefit you get from this effect is built-in current-limiting: what happens is that as the motor current increases during the on-time, you reach saturation where the FET will start limiting current. This in turn will limit torque, which is beneficial in most applications. For example, you don’t want your motor to shier cogs off of your drive-train.
The down-side is – again – efficiency: the FET does this in ‘linear’ mode, that is it limits the current by by increasing it’s source-drain voltage drop, thus burning more power.All in all, while you probably do want current-limiting in your design, it’s best left to the control circuit. That way you that can do it in ‘switched’ mode, not affecting efficiency.
The complementer CMOS driver, they use small FETs to drive bigger FET right? ThenIf that small FETs have low Rds, for example BSL316C L6327, Rds(on) 171mOhm will be problem?Or BSL316C L6327 they have both P and N, 177mOhm then will be problem?Suppose Battery = 12VDCmotor stall current = 1AThe calculate is I=Vbat/Rds then Ipeek = 12Vdc/(0.177+0.177) = 33.9A but that for short time.ton of P – N difference is 5ns, 3.4ns so it difference = 1.6ns, tooff is 14.3ns, 5.6ns so the difference is 8.6ns.If I try P= 12VDCx12DC/(0.177+0.177) x 8.6ns = 3.49uWattMeaning current is peek in short time (transition period), so heat dissipation is less. Not to be problem.
Am I right or wrong?Is that correct?Point is in my place, to find small P-FET with higher Rds is not easy. They only have P-Power FET. If this not work I might have to online order cost more money from some distant place. Cascading H-bridges is a really bad idea. For one, it will limit current delivery to the lowest of any of the bridges. On top of that it will most likely not work at all. Putting bridges in parallel might work, but there are a lot of pit-falls there as well, and driving them all with the same PWM input is a must.
The best way though is to have a single H-bridge, capable of driving the right amount of current. Since 3A and 1A are not all that different, can you maybe upgrade the power transistors in your old bridge to help with the increased current? Hi Andras, thanks for looking into this!I will inspect the type of FETS used in the DCC decoder, then mount stronger FETS either in place, or on a separated board and use them. As you said, the current requirements are not that drastically different, so the driver of the gates is probably capable of driving the more powerfull FETS. In fact, I might use the integrated H bridge that I ordered: half of an L298N.If I understand your answer correctly, you recommend to remove the FETS and protection diodes on the DCC decoder driver and then feed the DCC signals originally going to the gates of the (removed) FETS to the inputs of the H bridge: half of an L298N in my case. I have a unique problem I would like insight too.
It has been an electronic mystery to me – and ideas are running short. I have an H-Bridge design I am looking into. The rate of failure is less than 2%, but they want a fix. The device can run from a battery or wall adapter. When it fails, IT IS ALWAYS THE SAME lower N and not the P. There are several interesting things about this failure. The N has a higher Id rating than that of the P.
The bridge suffers from a conduction issue in its design. The switching on FETs input C feeds back to distort the unintended off leg – making for momentary conduction. Try as I might, though this happens ALL the time – I have been unable to prove this is the issue. And it does happen on both sides. When the N fails it always fails with a D-S short, but the G to D and G to S are also very low (typically less than 10 ohms). The bridge drives a motor.
The motor stalled can only draw.5A. When operated from wall adapter the wall adapter does not supply enough current even at its peak (SC) to be the issue. The SC current peaks at about 4.2A and the wall adapter folds back. What would be causes whereby I have the same FET to fail and not others. Hi!Of course it’s very difficult to give any advise without seeing the problem and doing experiments, but my first hunch would be that you violate the Vgs maximum rating on the device.
MOSFETs are very sensitive to this and even a momentary violation (that can happen due to capacitive coupling for example) can destroy the device. If I’m right (and as I’ve said, I could easily not be), the mitigation might be that you artificially decrease the impedance of the gate node of the FET so that the capacitive coupling doesn’t build up dangerously high voltages. You can do that by connecting a resistor between the FETs gate and source.As to why (again, predicated on me being right about the cause) this only impacts the low-side: P-channel MOSFETs for the same current rating (Rdson) are typically bigger then the equivalent N-channel device. This in turn means higher gate-capacitance. If there is indeed capacitive coupling, the parasitic capacitance and the gate capacitance forms a capacitive divider, which would result in a lower peak voltage on the P-channel part then in the N-channel for the same amount of aggression. So the N-channel device would see a Vgs violation sooner than the P-channel part would be.I hope this helps,Andras.
A million thanks for taking my question!!! Regarding paragraph 1 of your response a resistor added between the FET D and S, would have to be a very high value to not look like a leakage on condition. To decrease coupling back into the control circuit I introduced a resistor in the gate of the FET – there a sweet spot that has to be found that reduces the feedback, but does not overly slow the FET at stated PWM. It worked well in circuit and in simulation – though I would admit it looks a little strange in schematic. All the same my real goal is to find root cause of the problem.Regarding the second part of your response – I’m not quite following you.
Are you referring to a coupling path at the point of where the N and P Ds meet feeding back onto the Gs of said devices with the transient coming from the motor, or are you referring to a transient coming from the supply and being passed more effectively to the gate of the N. I am missing the cap divider concept here – assuming the parasitic cap you make reference to is the Cgd and CgsLastly not only is it the N that is failing it is always the same N (not the other). Hab,The idea is connect the resistor between the.gate.
and the source, not the drain. It appears you’re already working on a similar solution.The second paragraph was a theory as to why the low-side FET is going bust.
If you have noise coupling into the gate of (either) FETs capacitively, there is always a capacitive divider between that parasitic coupling capacitance and the gate capacitance (along with any other things connected to the gate, for example the driver output capacitance).For the same low-side FET to fail all the time – to state the obvious – there must be an asymmetry somewhere in the system. This might not be in the circuit though: for example if you mostly drive the motor in one direction, the circuit is used in an asymmetrical way, even if it itself is totally symmetrical.